Method of and apparatus for reducing current of semiconductor memory device
US5073874A · kind A · utility
22Cited by
17References
56Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 4, 1989 |
| Grant date | Dec 17, 1991 |
| Priority date | — |
| Expiry date | Oct 4, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A clock generator circuit of a dynamic RAM comprises a power-on reset circuit and an NOR gate connected to a RAS terminal and the reset circuit. In operation, the powre-on reset circuit generates a one-shot pulse immediately after the power supply is turned on. During a period of a pulse width of the one-shot pulse, this clock generator circuit operates as if it receives a high-level RAS signal and, as a result, it is possible to reduce an excessive current flowing into the dynamic RAM at the time of turning on the power supply.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.