Method and apparatus for testing memory
US5073891A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 14, 1990 |
| Grant date | Dec 17, 1991 |
| Priority date | — |
| Expiry date | Feb 14, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method and apparatus for testing the integrity of a memory storing controlled information. The data array semiconductor memory that stores controlled information such as instructions or microcodes, is partitioned into two halves. One half stores the test pattern information, the other half stores the test program. An instruction test (I-TEST) instruction is provided for testing the instruction cache data array. The test program comprises a pair of I-TEST instruction and checkerboard pattern forming an instruction equivalent to the width of the data array. The I-TEST instruction runs in dual instruction mode with a floating point instruction replaced by the test pattern. The I-TEST program is executed by transferring its test pattern data from the instruction cache data array to a register R1 in the register file, and then comparing that data with the expected value located in a register other than R1 in the register file. If any comparison fails, then a defect in the data array will have been detected. To fully cover the data array, the I-TEST program must be repeated with test patterns located in the other half of the data array and swapped by a swapper which is coupled to the d…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.