High voltage planar edge termination using a punch-through retarding implant and floating field plates
US5075739A · kind A · utility
41Cited by
4References
5Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 26, 1991 |
| Grant date | Dec 24, 1991 |
| Priority date | — |
| Expiry date | Feb 26, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/106
Abstract
A high voltage semiconductor structure having multiple guard rings is provided, wherein an enhancement region, which is of an opposite conductivity type from the guard rings, is formed between the guard rings to increase punch-through voltage between the guard rings. A floating field plate ring is formed over each guard ring, capacitively coupled to each guard ring. Each floating field plate has a flap extending beyond the guard ring in the direction of a main PN junction. The floating field plates serve to reduce parasitic coupling between adjacent guard rings.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.