Paired instruction processor precise exception handling mechanism
US5075844A · kind A · utility
45Cited by
5References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 24, 1989 |
| Grant date | Dec 24, 1991 |
| Priority date | — |
| Expiry date | May 24, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3861
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A mechanism for handling exceptions in a processor system that issues a family of more than one instruction during a single clock that utilizes the exception handling procedures developed for single instructions. The mechanism detects an exception associated with one of the instructions in the family, inhibits the data writes for the instructions in the family, flushes the pipeline, and reissues the instruction singly. The exception handling procedure for the single instruction may then be utilized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.