Memory access serialization as an MMU page attribute
US5075846A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 29, 1989 |
| Grant date | Dec 24, 1991 |
| Priority date | — |
| Expiry date | Sep 29, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0877
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processor having a serialization attribute on a page basis is provided. A set of page descriptors and transparent translation registers encode the serialization attribute as a cache mode. The data processor is a pipelined machine, having at least two function units, which operate independently of each other. The function units issues requests, for access to information stored in an external memory, to an access controller. The access controller serves as an arbitration mechanism, and grants the requests of the function units in accordance with the issuance order of the requests by the function units. When the memory access is marked serialized in the page descriptor, an access controller postpones the serialized access, until the completion of all pending memory accesses in the instruction sequence. All pending requests are then completed in a predetermined order, independent of the issuance order of the requests made by the function units, and all appropriate exception processing is completed. The postponed serialized access is then completed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.