Memory with a variable impedance bit line load circuit
US5075891A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 28, 1988 |
| Grant date | Dec 24, 1991 |
| Priority date | — |
| Expiry date | Nov 28, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A static random access memory (SRAM) includes a pair of p-channel metal-oxide-semiconductor (PMOS) transistors which serve as variable resistors for terminating bit lines and a control circuit for causing the PMOS transistors to have a low impedance level during read out and an intermediate impedance level during writing so that sudden d.c. current is suppressed and the voltage at the bit lines is prevented from being lowered. The variable resistor device can constitute a current mirror circuit along with a metal-insulator-semiconductor (MIS) transistor of the control circuit, so that it becomes possible to provide a stable control which is invulnerable to manufacturing tolerances.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.