Method of manufacturing a semiconductor device with a planar interlayer insulating film
US5077238A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 18, 1989 |
| Grant date | Dec 31, 1991 |
| Priority date | — |
| Expiry date | May 18, 2009 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/98
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing a semiconductor device in which an element is flattened by improving a technique of forming an interlayer insulating film. A thick insulating film having a film thickness necessary for a convexo-concave pattern to be flattened is deposited on a semiconductor substrate comprising the convexo-concave pattern of an element, a wiring and the like. Then, the thick insulating film is etched until it becomes a predetermined film thickness to form an interlayer insulating film having a predetermined film thickness from said thick insulating film. At this time, since acid and water are attached on the surface of the interlayer insulating film, a new film is formed on the surface of the interlayer insulating film to cover this water and acid. Then, a resist pattern having a desired configuration is formed on this new film. A contact hole is formed on the interlayer insulating film using this resist pattern. Thereafter, a wiring pattern electrically connected to the element is formed on the interlayer insulating film through the contact hole. According to this method, since the acid and water attached on the interlayer insulating film are covered with the new film, t…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.