Comparator circuit implemented in the bipolar and MOS technology
US5077489A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 1990 |
| Grant date | Dec 31, 1991 |
| Priority date | — |
| Expiry date | Oct 30, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45612
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An electronic comparator circuit having a high speed during switch phase and combining the advantages of bipolar technology with those of CMOS technology. The circuit consists of a differential stage input circuit having a differential pair of bipolar transistors forming its outputs. The output stage contains a pair of MOS transistors having gate electrodes in common. The pair of MOS transistors is connected on one side to the outputs of the input portion and on the other side to a positive supply pole via a current mirror circuit. The output contains another pair of MOS transistors with gate electrodes in common connected between the outputs of the input portion and ground. The drain electrode of the first pair of MOS transistors forms the output for the comparator.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.