VDMOS/logic integrated circuit comprising a diode
US5077586A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 26, 1990 |
| Grant date | Dec 31, 1991 |
| Priority date | — |
| Expiry date | Jul 26, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/811
Abstract
An integrated circuit includes a vertical power transistor, a depletion-mode lateral MOS logic transistor and a lateral Schottky diode in an N.sup.+ epitaxial semiconductor layer of an N substrate. The depletion-mode lateral transistor and Schottky diode are in a P well formed in the epitaxial layer during a first doping step. The vertical power transistor and depletion-mode lateral transistor include P.sup.+ semiconductor regions formed during a second doping step. The lateral transistor and Schottky diode include an N doped semiconductor channel layer formed during a third doping step so they have similar characteristics. The vertical power transistor includes a P doped semiconductor channel layer formed during a fourth doping step. The lateral transistor, Schottky diode and channel of the vertical power transistor include N.sup.30 doped semiconductor regions formed during a fifth doping step. The semiconductor region formed during the fifth step associated with the Schottky diode forms a ring around the layer of the diode formed during the third step. Metal electrodes are formed on regions of the transistors and diode as formed during the fifth step and on the diode layer formed…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.