Microprocessor control system having expanded interrupt capabilities
US5077662A · kind A · utility
10Cited by
9References
6Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Dec 22, 1989 |
| Grant date | Dec 31, 1991 |
| Priority date | — |
| Expiry date | Dec 22, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
To expand the interrupt capabilities of a microprocessor system without restructing system architecture, intermediate levels of priority are created for a given interrupt request. Plural interrupts can be handled on one interrupt request line to thereby permit execution of a number of functions that is greater than the number of interrupt lines. A system controller which provides this capabitlity can monitor the various functions during their execution, as well as arbitrate among plural interrupts so as to maintain the priority which has been assigned to them.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.