Dual framing bit sequence alignment apparatus and method
US5077794A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Mar 28, 1991 |
| Grant date | Dec 31, 1991 |
| Priority date | — |
| Expiry date | Mar 28, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L9/36
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A dual-framing-bit-alignment apparatus having a communications channel, a data device, an encryptor, a framing-bit device, a decryptor, a first framing-bit repositioner, and a second framing-bit repositioner. The first data device generates a first data-bit sequence having a first framing-bit sequence. The encryptor encrypts the first data-bit sequence as an encrypted-bit sequence. The framing-bit device substitutes on the encrypted-bit sequence, a second framing-bit sequence, thereby generating a framed-encrypted-bit sequence. The decryptor decrypts the framed-encryped-bit sequence as a second data-bit sequence. The second data-bit sequence contains errors due to the second framing-bit sequence. A second framing-bit repositioner detects in the second data-bit sequence, the first framing-bit sequence and the errors. In response to detecting the errors and the first framing-bit sequence, the first framing-bit repositioner aligns the first framing-bit sequence with the second framing-bit sequence.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.