Process for fabricating high performance BiCMOS circuits
US5079177A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 19, 1989 |
| Grant date | Jan 7, 1992 |
| Priority date | — |
| Expiry date | Sep 19, 2009 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/009
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of making complementary vertical bipolar transistors and complementary field effect transistors on the same substrate is described. The process includes forming buried layers in a semiconductor substrate which are spaced apart in a self-aligned manner by use of a lateral etching technique to undercut the mask used for definition of the buried layers. In the process, the collector and base contacts of the bipolar devices and the corresponding conductivity-type sources and drains of the field effect transistors are combined to minimize processing steps. The process also includes a silicided polycrystalline silicon layer used to form resistors and contact the various transistors.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.