Interpolating phase-locked loop frequency synthesizer
US5079520A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 7, 1991 |
| Grant date | Jan 7, 1992 |
| Priority date | — |
| Expiry date | Jan 7, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/1974
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The invention concerns are interpolating frequency synthesizer based on digital phase locking, with which frequencies can be produced which lie between frequencies defined by integer divisors. Traditional frequency synthesizers employ frequency dividers in which the dividing ratio is an integer. The circuit of the invention comprises member (8, 9), in one of which the reference frequency (f.sub.o) or the VCO frequency (f.sub.x), or the frequency obtained from them by division, is multiplied with a coefficient L and in the other member the corresponding frequency is multiplied by L+ .DELTA.L; and members (2, 7), in which the first pulses going to the phase detector (3) are lengthened by a time corresponding to a given integer number k1 of pulses formed in the number (8), and the other pulses are lengthened by a time corresponding to a given integer number k2 of pulses formed in the member (9).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.