Transformerless power monitor circuit having means for electronically latching DC alarms
US5079688A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 13, 1990 |
| Grant date | Jan 7, 1992 |
| Priority date | — |
| Expiry date | Dec 13, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/30
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a power monitor circuit, AC power-line voltage is converted by a DC power supply to a regulated DC voltage. The DC power supply shuts down itself in the event of a failure therein. The output of DC supply rises from zero to a specified value in slow response to power-on state and drops to zero in slow response to a significant drop in the AC voltage. A rectifier-filter converts the AC voltage to a nonregulated DC voltage. The output of the rectifier-filter rises in quick response to the power-on state and drops in quick response to the significant AC voltage drop. If the output of DC power supply drops below a specified theshold due to AC power-line failure or due to its own failure, a DC low-voltage signal is generated. If the output of rectifier-filter rises above a specified low level a first AC transitory signal is generated and if it drops below a specified high level a second AC transitory signal is generated. A latch circuit is energized with the nonregulated DC voltage to latch the DC low-voltage signal if it occurs during the interval between the first and second AC transitory signals and supplies a DC alarm signal to computer circuitry. A power controller is energized …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.