Bidirectional FIFO buffer having reread and rewrite means
US5079693A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 28, 1989 |
| Grant date | Jan 7, 1992 |
| Priority date | — |
| Expiry date | Feb 28, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2205/067
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A FIFO buffer in accordance with the present invention employs a 1K by eighteen FIFO (A.fwdarw.B) buffer portion to store eighteen-bit words; an eighteen-bit-to-nine-bit multiplexer portion to convert (fold) stored eighteen-bit words into two, nine-bit words; a nine-bit-to-sixteen-bit multiplexer portion to convert (assemble) pairs of nine-bit words into one, eighteen-bit word; a 1K by eighteen FIFO (B.fwdarw.A) buffer portion to store (eighteen-bit) words; eighteen, tri-state, buffers to permit direct communication; a parity generator portion; a parity checking portion; the combination of an A-port access control portion and a programmable flag logic portion to permit connection to a sixteen-bit or a thirty-two-bit microprocessor; and the combination of a B-port access control portion and a hand shake interface control portion to permit connection to an eight-bit microprocessor, a non-direct memory access DMA type peripheral device, or a DMA-type peripheral device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.