Memory management unit for the MIL-STD 1750 bus
US5079737A · kind A · utility
109Cited by
5References
4Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Oct 25, 1988 |
| Grant date | Jan 7, 1992 |
| Priority date | — |
| Expiry date | Oct 25, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/364
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A single-chip memory management unit automatically operates in either 1750A or 1750B mode as required, including the provision of memory management and/or block protection, with the added feature of on-chip arbitration between two bus masters that may be either independent of the CPU or controlled by the CPU.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.