Semiconductor memory circuit
US5079746A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 7, 1989 |
| Grant date | Jan 7, 1992 |
| Priority date | — |
| Expiry date | Feb 7, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C17/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory circuit comprises a plurality of memory cells and a plurality of programming transistors, each memory cell being provided at the intersections of one bit line and one word line. The memory cell includes an insulator and a cell transistor, and a conductivity type of the cell transistor selected by a word line select signal is opposite to that of the programming transistor selected by a bit line select signal. The memory cell is programmed by utilizing an electrical breakdown of the insulator, when the bit line select signal and the word line select signal supplied are in-phase and both the programming transistor and the cell transistor are switched. Therefore, the memory cell is programmed in a short time during which the programming transistor and the cell transistor are switched, and thus this semiconductor memory circuit can be programmed with a low consumption of power and of a high speed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.