Semiconductor integrated circuit device
US5081515A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 20, 1990 |
| Grant date | Jan 14, 1992 |
| Priority date | — |
| Expiry date | Mar 20, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/13091
Abstract
A semiconductor integrated circuit device is equipped with a DRAM whose memory cell is formed as a series circuit of a memory cell selection MISFET and a data storage capacitance element of a stacked structure. A complementary data line extends on an upper electrode layer of the data storage capacitance element of the stacked structure through an inter-level insulation film which is connected to a semiconductor region of the memory cell selection MISFET. To reduce parasitic capacitance the wiring width of the complementary data line is formed to be smaller than the film thickness of the inter-level insulation film between the complementary data line and the upper electrode layer of said data storage capacitance element of the stacked structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.