Branch control in a three phase pipelined signal processor
US5081574A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 26, 1990 |
| Grant date | Jan 14, 1992 |
| Priority date | — |
| Expiry date | Feb 26, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3842
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The architecture and instructions of the processor utilized in the present invention permit efficient accomplishment of signal processing tasks. A three phase pipelined operation for instructions exists consisting of fetch, decode, and execute operations. To provide additional flexibility and reduce branch latency, all of the instructions executed except for branch instructions are executed on phase three. Branch instructions are caused to execute at the end of phase two. The branching conditions may be on the basis of "hot bits" existing within the processor during the second cycle and resulting from the execution of the instruction just preceding the branch instruction. Conditional branches are performed based upon conditions not previously latched into registers that result from the execution of such instructions. These conditions are generated at the same time that the branch will be executed. The conditions which may be used to trigger a branching decision may also result from the ALU operation output or from the state of a selected data bus bit. The instructions providing the branch conditions must not be separated from the associated branch instruction. Therefore, to prevent…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.