Arithmetic logic unit
US5081607A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 23, 1990 |
| Grant date | Jan 14, 1992 |
| Priority date | — |
| Expiry date | Feb 23, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3828
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A digital arithmetic logic unit in which the carry chain is subdivided into a series of bit fields allowing independent and simultaneous data manipulation to be undertaken in each of the bit fields. Division of the carry chain is achieved via a carry chain selector consisting of a series of multiplexers, one being placed between each pair of adjacent stages of the carry chain. Each multiplexer has two data inputs, one of which forms the carry to the next stage of the carry chain. The carry selected either continues the computation or defines the end of one bit field and provides the least significant carry-in bit to the next bit field. This selection of the carry by the multiplexer is under control of a programmable register, thus allowing variable division of the carry chain.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.