Parallel bit detection circuit for detecting frame synchronization information imbedded within a serial bit stream and method for carrying out same
US5081654A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 12, 1989 |
| Grant date | Jan 14, 1992 |
| Priority date | — |
| Expiry date | May 12, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/5672
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A parallel frame synchronization circuit converts an incoming serial bit stream containing frame synchronization information into parallel data words on arbitrary boundaries of fixed bit length. Detectors forming part of the present invention determine from the parallel converted data the presence of synchronization information so as to align the incoming serial data into parallel data aligned on frame boundaries by manipulating parallel words. The present invention is particularly suited for fabrication in complimentary metal oxide silicon (CMOS) technology and in a preferred embodiment is used to synchronize incoming data comporting to the synchronous optical network (SONET) telecommunication standard.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.