System for controlling data transfer using transfer handshake protocol using transfer complete and transfer inhibit signals
US5081701A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 11, 1989 |
| Grant date | Jan 14, 1992 |
| Priority date | — |
| Expiry date | Oct 11, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/423
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit for controlling data transfer handshake protocol so that certain protocol events may occur prior to or simultaneously with the completion of a proceeding protocol event, and the ultimate results of the pending protocol event may be determined at a later time. In one embodiment of the invention a CPU operates to transfer data (either receive or send) between itself and an I/O channel every five processor clock cycles. At the beginning of each set of five clock cycles the CPU places data on the data bus and generates a transfer request (CPU-XFR) signal whenever it receives a data accepted (DATA-ACC) signal indicating that a previous data transfer has occurred. The CPU-XFR signal is generated regardless of whether or not the previous data transfer is complete at the time. The data transfer normally is completed one clock cycle after the CPU-XFR signal is generated, and at that time a transfer complete signal is generated. If the transfer complete signal is not generated, a transfer inhibits signal is generated for inhibiting the generation of the succeeding DATA-ACC signal and hence the next CPU-XFR signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.