Signal clamp circuitry for analog-to-digital converters
US5084700A · kind A · utility
18Cited by
10References
11Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 4, 1991 |
| Grant date | Jan 28, 1992 |
| Priority date | — |
| Expiry date | Feb 4, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/124
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Clamping circuitry for adjusting the D.C. voltage of a signal which is A.C. coupled to an ADC includes D.C. level adjusting circuitry coupled to the input of the ADC. Logic circuitry, responsive to a single bit of output samples provided by the ADC, provides control signals to the D.C. level adjusting circuitry, to condition the D.C. level adjusting circuitry to adjust the D.C. level of the A.C. signal to a desired value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.