Plural-order sigma-delta analog-to-digital converter using both single-bit and multiple-bit quantizers
US5084702A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 1, 1990 |
| Grant date | Jan 28, 1992 |
| Priority date | — |
| Expiry date | Nov 1, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M3/414
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An oversampling converter of a type using a plural-order, plural-stage sigma-delta modulator, the output signal to the decimating filter of which modulator has the quantization noise contribution of a number of its plurality of stages suppressed therein, uses single-bit quantization in those stages, and the modulator uses single-bit quantization in those stages. Those stages each employ digital-to-analog converters with single-bit resolution in their feedback connections to avoid non-linearity problems. Another sigma-delta converter stage, the quantization noise of which appears in substantial amount in the converter output signal to the decimating filter, uses quantization having multiple-bit resolution to help increase the resolution of the oversampling converter overall. This other sigma-delta converter stage also employs a digital-to-analog converter with single-bit resolution in its feedback connection in order to avoid non-linearity problems, with additional circuitry being used to compensate for the digital-to-analog converter having single-bit, rather than multiple-bit, resolution.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.