Precision digital-to-analog converter
US5084703A · kind A · utility
3Cited by
6References
9Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 12, 1991 |
| Grant date | Jan 28, 1992 |
| Priority date | — |
| Expiry date | Apr 12, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/785
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital-to-analog converter is disclosed which employs a ladder configuration comprising a series of R1-R2-R3 stages in which resistors R2 and R3 are selected so that mathematically the combined resistance of R2 in parallel with R3 is equal to twice the resistance of R1. The resistance of resistor R3 is on the order of 3 to 30 times greater than the resistance of resistor R2. These resistors are configured in stages with FET switches.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.