Method and apparatus for hidden surface removal
US5084830A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 26, 1987 |
| Grant date | Jan 28, 1992 |
| Priority date | — |
| Expiry date | Oct 26, 2007 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06T15/405
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device having a plurality of addressable memory locations, each of which can be defined uniquely by an address word having an X component and a Y component, which memory locations correspond respectively to grid points in a rectangular array at a pitch dX in the X direction and a pitch dY in the Y direction, is loaded with data values Q. In a first operating cycle, a first address word defining a memory location corresponding to a first grid point is generated. In a second cycle, a first value of Q as a function of X and Y is computed, and concurrently a second address word defining a memory location corresponding to a second grid point is generated. In a third cycle, the first value of Q is compared with a previous value of Q for the first grid point, and concurrently a third address word defining a memory location corresponding to a third grid point is generated and a second value of Q is computed. In a fourth cycle, the first value of Q is loaded into the memory location corresponding to the first grid point if that first value of Q bears a predetermined relationship to the previous value of Q.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.