Chip carrier
US5086334A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 25, 1991 |
| Grant date | Feb 4, 1992 |
| Priority date | — |
| Expiry date | Apr 25, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/3011
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit chip carrier having reduced and predicable interlead capacitance, reduced glass chip formation, and improved wirebonding characteristics is disclosed. The chip carrier includes a substrate having a central cavity for locating an integrated circuit die, an inner channel and an outer channel, adhesive glass located in the channels and overflowing above the substrate surface, a leadframe mounted on the substrate having a plurality of leads embedded in the adhesive glass overflow and coplanarly resting on the substrate, the leads extending from beyond the substrate periphery inward to near the cavity rim, and a thin layer of sealing glass extending from the periphery of the substrate over the outer channel for hermetically sealing the chip carrier.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.