Sense amplifier and method for ferroelectric memory
US5086412A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 21, 1990 |
| Grant date | Feb 4, 1992 |
| Priority date | — |
| Expiry date | Nov 21, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A ferroelectric random access memory device contains columns of ferroelectric memory cells, each column of memory cells being coupled to a distinct bit line. Each memory cell is selectively coupled to a corresponding bit line by an access control transistor so that only one memory cell in the column is coupled to the bit line at a time. To read the data stored in a selected memory cell reads, the cell is strobed twice, separately sampling the output voltage generated each time. Since the first read is a destructive read, the second read operation always reads the cell in its "0" state. Then the two sampled outputs are compared, and if the first reading exceeds the second by at least a threshold amount then a "1" output value is generated. Otherwise a "0" is the output value. In a preferred embodiment, the time delay between strobing the memory cell and sampling its output is made longer the first time that the cell is read than for the second time that the cell is read. In this way, if the cell is storing a "0" bit, the first read will produce an output voltage that is smaller than it would have been had the first read not been delayed, which helps to ensure that cells storing "0" …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.