Fault-tolerant digital computing system with reduced memory redundancy
US5086429A · kind A · utility
44Cited by
12References
2Claims
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Key dates
| Filing date | Apr 10, 1990 |
| Grant date | Feb 4, 1992 |
| Priority date | — |
| Expiry date | Apr 10, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/2043
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A highly reliable data processing system using the pair-spare architecture obviates the need for separate memory arrays for each processor. A single memory is shared between each pair of processors wherein a linear block code error detection scheme is implemented with each shared memory, wherein the effect of random memory faults is sufficiently detected such that the inherent fault tolerance of a pair-spare architecture is not compromised.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.