Method of stacking semiconductor substrates for fabrication of three-dimensional integrated circuit
US5087585A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jul 11, 1990 |
| Grant date | Feb 11, 1992 |
| Priority date | — |
| Expiry date | Jul 11, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/19041
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor substrate stacking method comprises the steps of preparing first and second thin film devices each in the form of a thin film having a connection electrode formed on an upper surface thereof and a connection electrode formed on an undersurface thereof, each of the thin film devices being bonded at its upper surface thereof to a support plate by adhesive. The first thin film device is stacked and bonded onto a base substrate having a device formed thereon and a connection electrode formed on the device, in such a manner that the device formed on the base substrate faces the undersurface of the first thin film device and the connection electrode formed on the device formed on the base substrate is in alignment with and in contact with the undersurface connection electrode formed on the first thin film device. The support plate and the adhesive of the first thin film device are removed so that the upper surface of the first thin film device and the upper surface connection electrode formed on the upper surface of the first thin film device are exposed. Similarly, the second thin film device is stacked and bonded onto the first thin film device stacked on the base subst…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.