Timing circuit for single line serial data
US5087828A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 12, 1991 |
| Grant date | Feb 11, 1992 |
| Priority date | — |
| Expiry date | Feb 12, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/135
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A timing adjusting circuit for single line serial data includes a synchronous data sampling circuit for sampling data input from the exterior synchronously with a reference clock pulse, a data edge detection circuit for outputting data edge detection signals, and a synchronous pulse generation circuit for generating repetitive pulses synchronized with output from the data edge detection circuit. The timing circuit further includes an inversion circuit for inverting branched part of the reference clock pulse, a sub-data sampling circuit for sampling the branched data at the inverted reference clock pulse, a sub-data edge detection circuit for outputting edge detection signals synchronized with the inverted reference clock pulse, a sub-synchronous pulse generation circuit for generating repetitive pulses synchronized with output from the data edge detection circuit, an adder for performing logical addition of output of the synchronous and sub-synchronous pulse generation circuits, an adder for performing logical OR of output of the data sampling and edge detection circuits, a waveform shaping circuit for eliminating extraneous signals, and an output timing circuit for adjusting timin…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.