High speed clock distribution system
US5087829A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 1, 1989 |
| Grant date | Feb 11, 1992 |
| Priority date | — |
| Expiry date | Dec 1, 2009 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/15
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
This invention discloses a clock distribution system which distributes a first clock signal as a reference clock as the reference for the phase and frequency to each processing unit (e.g. LSI) and generates a multi-phase second clock signal to be used in each processing unit by a delay circuit group whose delay time is adjusted. The clock distribution system comprises a clock generation block for generating a one-phase reference clock; a first control loop for comparing the phase of the reference clock with the phase of a feedback signal and adjusting the phase of the reference clock so that their phases are in agreement; and a second control loop including a delay circuit group consisting of a plurality of variable delay circuits to which the reference clock phase-adjusted by the first control loop is inputted and which are connected in series, and means for generating a multi-phase clock signal by use of the output signal of each of the plurality of variable delay circuits and the phase-adjusted referencde clock, controlling the delay time of the plurality of variable delay circuits so as to accomplish a predetermined relation with the period of the phase-adjusted reference clock…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.