Integrated output buffer logic circuit with a memory circuit
US5087840A · kind A · utility
13Cited by
9References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 13, 1991 |
| Grant date | Feb 11, 1992 |
| Priority date | — |
| Expiry date | Feb 13, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/106
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit having logic circuits and a logic output buffer, which circuit includes the following sub-circuits: a memory circuit and a logic output circuit, in which no tri-state occurs at the output during a sequence of data signals at the input, wherein the drive of the circuit by means of control signals is not critical over time because the first data signal from the sequence switches off the tri-state mode, the tri-state mode again being introduced if a control signal is furnished, and in the absence of this control signal, the last data signal is retained.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.