TTL to CMOS translating circuits without static current
US5087841A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 9, 1990 |
| Grant date | Feb 11, 1992 |
| Priority date | — |
| Expiry date | Apr 9, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K3/3565
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
TTL to CMOS level translating buffer circuits incorporate multiple stages with feedback and forward couplings between stages that eliminate static current I.sub.cct when TTL high potential level data signal is applied at the buffer circuit input. The feedback and feed forward couplings maintain and enhance signal propagation speed in the buffer circuits at the same time. TTL to CMOS translating latch circuits and flip-flop circuits similarly incorporate feedback and feed forward circuit couplings to save and retain data signals during latch mode, static mode, and tristate mode operation while at the same time substantially eliminating static high current I.sub.cct. The clock circuit portions for the latch and flip-flop circuits also are arranged in clock circuit configurations that are free of static current I.sub.cct.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.