Input/output processor control system with a plurality of staging buffers and data buffers
US5088025A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 21, 1989 |
| Grant date | Feb 11, 1992 |
| Priority date | — |
| Expiry date | Feb 21, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/372
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A control system for multiple channel data transfers between a main bus and a data bus is provided. A novel input/output processor control which permits multiple word transfers to occur in a single predetermined time slot while resolving buffer access conflicts and includes staging buffers coupled to the main bus and data buffers coupled to the data bus. A J-Bus is coupled between the staging buffers and the data buffers and is controlled by J-Bus transfer controller. A D-Bus transfer controller controls information transferred to an from the data bus and the data buffers. An M-Bus transfer controller controls information transferred to and from the staging buffers and the M-Bus. A controllable time slot generator in addition to generating the time slots for transferring information between the data buffers on the J-Bus also provides means for resolving conflicts between the J-Bus and the D-Bus and the M-Bus.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.