Process for attaching large area silicon-backed chips to gold-coated surfaces
US5089439A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 2, 1990 |
| Grant date | Feb 18, 1992 |
| Priority date | — |
| Expiry date | Feb 2, 2010 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T428/12528
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for eutectically attaching a silicon chip to a gold-coated substrate. Prior to heating and scrubbing of the silicon chip against the gold surface, a gold lattice structure is placed between the silicon chip bottom surface and the gold surface. The gold lattice structure contacts the silicon chip bottom surface over an area equal to less than ten percent of the total surface area of the chip bottom surface. The point source contact between the gold lattice and silicon chip promotes formation of the gold/silicon eutectic alloy at temperatures of between 400.degree. to 475.degree. C. The gold/silicon eutectic alloy spreads between the silicon chip bottom surface and gold top surface to provide eutectic bonding. The method is especially useful in bonding relatively large silicon chips or dies to gold-coated substrates wherein the bottom surface or back side of the chip is not coated with a protective metal layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.