CMOS-based pseudo ECL output buffer
US5089723A · kind A · utility
13Cited by
3References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 15, 1990 |
| Grant date | Feb 18, 1992 |
| Priority date | — |
| Expiry date | Nov 15, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018521
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The present invention provides a CMOS output buffer with ECL output characteristics that allows the outputs to be terminated in any manner desired and which is not limited by the op amp settling time. The buffer establishes a bus internally for the VOH and VOL levels and then switches between the buses using transmission gates. In the disclosed embodiment of the invention, the op amp's feedback path includes a P-channel device which is either identical to or, to conserve power, a carefully scaled down equivalent of the P-channel output device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.