Cache providing caching/non-caching write-through and copyback modes for virtual addresses and including bus snooping to maintain coherency
US5091846A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Oct 30, 1989 |
| Grant date | Feb 25, 1992 |
| Priority date | — |
| Expiry date | Oct 30, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/502
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computing system, having a cache-memory management system, provides selectable access modes for addressable memory, providing cacheable and noncacheable access modes, definable on a fixed page boundary basis. The various access modes can be intermixed on a page by page basis within the translation logic of the cache-memory management system. The cache-memory management system provides high speed virtual to real address translation along with associated system tag data defining access priorities and access modes associated with each respective address translation. The selectable access modes provides software definable features, such as cacheable data or non-cacheable data, write-through or copyback main memory update strategies for cacheable data, and real memory address space selection as main memory real address space, versus Boot ROM real address space versus input/output real address space. Page tables are loaded into main memory which contain address translation data and associated system tags. Upon initialization of the modifiable translation logic in the cache-memory management system, the address translations and associated system tags are loaded into the address translat…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.