Vector processor for merging vector elements in ascending order merging operation or descending order merging operation
US5091848A · kind A · utility
42Cited by
12References
38Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 11, 1988 |
| Grant date | Feb 25, 1992 |
| Priority date | — |
| Expiry date | Apr 11, 2008 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/22
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Vector elements are compared in synchronism with the supplying of vector elements to the an operation unit for merging, and the operation to be effected on the individual vector elements is selected depending upon the compared results. A break is detected between elements arranged in ascending order and elements arranged in descending order, and the merging of the vector elements subsequently read is effected for either ascending order elements or descending order elements depending upon the detected result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.