Processing method for fabricating electrical contacts to mesa structures in semiconductor devices
US5093225A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 14, 1990 |
| Grant date | Mar 3, 1992 |
| Priority date | — |
| Expiry date | Sep 14, 2010 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S438/948
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor mesa structure is covered with a photoresist material in a localized flooding manner such that the photoresist material is thinner on the top of the mesas and also at the upper most portion of the sidewalls than at the base of the mesa and the intervening channel. The photoresist is then exposed through a mask in a manner so that when developed, the photoresist from the mesa top and upper most portion of the sidewall can be removed. When the photoresist is exposed to the actinic radiaction, the thinner photoresist is adequately exposed more rapidly than the thicker portion nearer the bottom of the mesa, if the mask does not adequately shield the actinic radiation from reaching it. Thus the alignment tolerance is greater than if the photoresist were of uniform thickness.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.