Method of making a semiconductor device having lead pins and a metal shell
US5093282A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 29, 1991 |
| Grant date | Mar 3, 1992 |
| Priority date | — |
| Expiry date | Jan 29, 2011 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/4913
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is a method for making a semiconductor device in which the Pin Grid Array (PGA) is improved so that a plurality of lead pins project from the undersurface of a metal base of a package substrate as input and output terminals of a Large Scale Integrated-circuit (LSI). The method comprises mounting a semiconductor chip on a heat sink to the base, superposing a printed circuit board on the base and connecting electrical lead pins to the outer ends of wiring patterns which are formed radially and downwardly projecting through the base, and assembling a metal shell to the upper surface of the base and covering the chip, bonding wires and wiring patterns, wherein the patterns are formed such that the outer ends of the patterns are located within the vicinity over the outermost rows and columns of through holes for connecting lead pins. Furthermore, in the method of producing the device, a central portion patterning wiring layer, which is electrically short-circuited for gold plating, is provided in order to stabilize the connection with the bonding wires, and this center layer is cut off after the short circuit is performed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.