Latched accumulator fractional N synthesis with residual error reduction
US5093632A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Aug 31, 1990 |
| Grant date | Mar 3, 1992 |
| Priority date | — |
| Expiry date | Aug 31, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/1976
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A latched accumulator fractional-N synthesizer having reduced residual error for use in digital radio transcievers is disclosed. The divisor of the frequency divider (103) of the synthesizer is varied with time by the summation of accumulator carry output digital sequences which result in frequency increments equal to a fraction of the reference frequency. The accumulators (615,617) are latched such that upon the occurrence of a clock pulse, data is transferred through each accumulator one clock pulse step at a time, such that the delay through the system is equal to that of only one accumulator. The latched output of the second highest order accumulator (619) is subtracted from the latched output of the highest order accumulator (621) and differentiated before being applied to the loop filter (109).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.