Clock acquisition in a spread spectrum system
US5093841A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 30, 1990 |
| Grant date | Mar 3, 1992 |
| Priority date | — |
| Expiry date | Jan 30, 2010 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04B1/707
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A circuit and method is disclosed for recovering the transmitter clock at a receiver in a direct sequence spread spectrum communication system where a transmitter and receiver run independent clocks of nominally the same frequency. At the receiver, to select the phase of the local clock that yields the strongest signal, a clock recovery circuitry cycles through M phases of the locally generated receiver clock. The cycling is halted and the phase is locked soon as an indication is obtained that a phase is valid. Alternatively, all M phases of the local clock are tested for validity or invalidity, and depending on the resulting pattern of valid and invalid phases, a particular phase is selected for the local clock. A phase is valid or invalid depending on whether there is a second correlation crossing at the expected instant one data bit period after a first correlation crossing.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.