Method and apparatus for executing instructions in a single sequential instruction stream in a main processor and a coprocessor
US5093908A · kind A · utility
33Cited by
12References
16Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 17, 1989 |
| Grant date | Mar 3, 1992 |
| Priority date | — |
| Expiry date | Apr 17, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3877
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A tightly-coupled main processor and coprocessor overlap the execution of sequential instructions when apparent sequential operation and precise exception interrupts can be assured. Logic detects all conditions under which these criteria might potentially be violated in the coprocessor before it has finished performing an instruction, and holds off the main processor from executing a subsequent instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.