Method for manufacture of an integrated MOS semiconductor array

US5094983A · kind A · utility

Assignee

• Telefunken Electronic GmbH · DE

Inventors

• Josef Furthaler · Heilbronn, DE
• Friedemann Gschwend · Heilbronn, DE
• Manfred Ohagen · Untergruppenbach, DE
• Peter Tomaszewski · San Jose, US

Key dates

• Filing date: Oct 9, 1990
• Grant date: Mar 10, 1992
• Expiry date: Oct 9, 2010

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/0002
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method of manufacture of an integrated MOS semiconductor array for the low-frequency range having MOS components and circuit paths arranged on a semiconductor substrate. Exposed surfaces between the circuit paths are made hydrophobic by germinating with hexamethyl disilazane ((CH.sub.3).sub.3 SiNHSi(CH.sub.3).sub.3), so that the occurrence of leakage currents is avoided. In addition, in an integrated MOS semiconductor array in which the MOS components and the circuit path are covered with a protective layer, the surface of this protective layer is made hydrophobic. As a result, both leakage currents and parasitic capacitances are prevented.