Circuits for preventing breakdown of low-voltage device inputs during high voltage antifuse programming
US5095228A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Apr 19, 1991 |
| Grant date | Mar 10, 1992 |
| Priority date | — |
| Expiry date | Apr 19, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00315
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit for isolating a first low-voltage circuit mode from a second circuit node which carries high programming voltages during programming of user-programmable interconnect elements includes a novel two input NAND gate having one input structure configured from high voltage devices connected to the second circuit node. The other input of the NAND gate is a control input for the isolation device and is connected to a low-voltage logic signal which is high when the signal from the high programming voltage node is to be passed through to the low-voltage node and low when the low-voltage node is to be isolated from the high programming voltage node. The output of the NAND gate is connected to the first low-voltage circuit node.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.