Cache flush request circuit flushes the cache if input/output space write operation and circuit board response are occurring concurrently
US5095428A · kind A · utility
8Cited by
7References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 4, 1989 |
| Grant date | Mar 10, 1992 |
| Priority date | — |
| Expiry date | Jan 4, 2009 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0835
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer system which flushes the cache controller when a circuit board is being configured or is responding to an input/output write operation. The flush operation can be disabled for each circuit board location. A cache flush operation can also be directly requested.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.