Binary multiplier circuit with improved inputs
US5095455A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 6, 1990 |
| Grant date | Mar 10, 1992 |
| Priority date | — |
| Expiry date | Sep 6, 2010 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/4812
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A binary multiplier circuit has a logic operator acting as an exclusive-OR gate generating a first intermediate signal which is an exclusive-OR of a first input and a carry-in input. An inverter generates a second intermediate signal. A second logic operator generates a first output bit which is a symmetrical exclusive-OR of a second input and both the first and second intermediate signals. A second output bit is a symmetrical trigger function of the first and second input, depending on the first and second intermediate signals, and is generated in a transmission gate. Since the carry-in signal passed via the first and second intermediate signals is applied directly to transistors of the transmission gate, carry propagation delay is reduced. A fixed operand is multiplied by a variable operand by storing a partial result of the multiplication using an accumulator and a shift register with the binary calculation circuit. A two-input multiplexer has one of its inputs connected to the output from the register and an output connected to the input of the register. The variable operand is applied serially to a control input of the multiplexer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.