Buffer circuit used in a semiconductor device operating by different supply potentials and method of operating the same
US5097152A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 10, 1991 |
| Grant date | Mar 17, 1992 |
| Priority date | — |
| Expiry date | Jan 10, 2011 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018585
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
In an output buffer circuit, two P channel MOSFET's (1, 2) are connected in parallel between a power supply terminal (16) and an output terminal (10), and two N channel MOSFET's (3, 4) are connected in parallel between the ground terminal (17) and the output terminal (10). When a normal power supply potential is applied to the power supply terminal (16), either one of the P channel MOSFET's (1, 2) or either one of N channel MOSFET's (3, 4) is turned on in response to an input signal. When a high potential is applied to the power supply terminal (16), two P channel MOSFET's (1, 2) or two N channel MOSFET's (3, 4) are turned on in response to the input signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.