Circuitry for compensating for transistor parameter mismatches in a CMOS analog four-quadrant multiplier
US5097156A · kind A · utility
4Cited by
7References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 11, 1991 |
| Grant date | Mar 17, 1992 |
| Priority date | — |
| Expiry date | Apr 11, 2011 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06G7/163
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present invention provides a circuit for eliminating quadratic and offset errors in the output of a CMOS four-quadrant analog multiplier. These errors are eliminated by feedback circuits that each include one or more CMOS four-quadrant analog multipliers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.